Line (output) driver circuits providing on-chip termination (i.e. using its output impedance as termination) are capable of delivering the same voltage swing with half of the power when compared with line drivers using external resistor termination. This power advantage arises because the on-chip termination line driver does not need to drive the external termination resistor.
FIG. 9 shows a basic prior art line driver circuit 30 that produces a controlled termination resistance ROUT using voltage and current feedback. Line driver 30 is disclosed in U.S. Pat. No. 5,121,080, which is incorporated herein by reference in its entirety. Line driver 30 includes an amplifier 31 having an inverting input terminal connected to ground (or a common mode voltage), a non-inverting input terminal connected to a current driver 32, and an output terminal connected to a node 34. Current driver 32 includes a digital-to-analog converter (DAC) that generates a current signal IDAC derived from an input signal received from a logic portion of the integrated circuit (not shown) on which line driver 30 is incorporated. Node 34 is connected to drive the gate terminals of a first P-channel transistor 36 and a second P-channel transistor 37. The source-drain path of first P-channel transistor 36 is connected between voltage source VDD and an internal node 38, and the source-drain path of second P-channel transistor 37 is connected between voltage source VDD and an output node 39, at which output voltage VOUT is generated. Input node 38 is connected to the non-inverting input terminal of amplifier 31 and to current driver 32, and a feedback resistor Rf is connected between nodes 38 and 39.
In operation, line driver 30 is implemented to transmit data signals to a selected signal destination by way of a transmission line, which is represented in FIG. 9 by a load resistor RL that is connected between the output node 39 and ground. First transistor 36 forms the first stage of a current drive circuit that generates a current I1 in response to the output signal generated by amplifier 31, and transistor 37 forms a second stage that is a “replica” of the first stage in that it is also driven by the output signal from amplifier 31, and generates a current I2 that is directly proportional to current I1 of the first stage. A ratio between the two currents I1 and I2 generated by the two drive stages corresponds to an aspect ratio between transistors 36 and 37, which is set such that first transistor 36 is given a value of “1” and second transistor 37 is given a value of “N”. The output impedance of amplifier 31 is a function of the current ratio between transistors 36 and 37, as well as the value of the feedback resistor Rf. This relationship provides a constant ratio between the current drive and the output current. In essence, current drive is added to the summing node utilizing a replica of the first output stage, with the output impedance depending upon the on-chip feedback resistance Rf such that adjustment of either the feedback resistor Rf or the value of “N” will allow adjustment of the output impedance, as represented below by Equation 1:ROUT=Rf/(1+N)  Eq. 1Meanwhile, the transimpedance gain of driver circuit 30 is represented by Equation 2:VOUT=IDAC*(N*RL)/2  Eq. 2Note that Eq. 2 is true if Rf=(1+N)*RL, and Eq. 1 is satisfied.
A problem with line driver 30 is that the on-chip resistor Rf is subjective to process variation, and as a result, the output resistance ROUT will vary from chip to chip. Avoiding this problem requires a mechanism for adjusting the output resistance ROUT after fabrication in order to cause output resistance ROUT to match load resistance RL. From Equation 1, to make the output resistance ROUT adaptive, those skilled in the art will recognize that the best approach is to control (adjust) the values Rf or N, or both.
FIG. 10 shows another prior art line driver 40 that achieves a consistent output resistance by utilizing a variable replica stage 47 to adjust the value of N in Eq. 1 (above). Output driver circuit 40 is disclosed in U.S. Pat. No. 7,119,611 issued Oct. 10, 2006, which is incorporated herein by reference in its entirety. Similar to line driver 30 (discussed above), line driver 40 includes an amplifier 41 having an inverting input terminal connected to ground, a non-inverting input terminal connected to a current driver 42, and an output terminal connected to drive the gate terminals of a first stage P-channel transistor 46. The source-drain path of first P-channel transistor 46 is connected to an internal node 48. Variable replica stage 47 includes multiple transistors programmably connected in parallel such that their source-drain paths selectively connected between VDD and output node 49, which in operation is connected to a transmission line represented in FIG. 10 by a load resistor RL. Internal node 48 is connected to the non-inverting input terminal of amplifier 41 and to current driver 42 by way of a feedback resistor RF, and a series resistor RS is connected between internal node 48 and output node 49. The current through variable replica stage 47 is a function of the number of transistors that are connected in parallel, which is controlled by a value stored in a calibration register (not shown). This value is determined by an analog engine during a calibration operation, which determines the value of the output impedance ROUT as a function of the series resistance RS and the ratio of transistor 46 and the selected parallel transistors in variable replica stage 47. The ratios of the transistor 46 and the parallel connected transistors in variable replica stage 47 are defined such that a value of “1” is assigned for the transistor 46 and a value of “N” is assigned for the selected transistors in variable replica stage 47, it being understood that the value of “N” can be varied by selecting different combinations of transistors in variable replica stage 47.
Although line driver 40 provides advantages over line driver 30 (see FIG. 9), it still presents a few problems. First, the variable replica stage arrangement provides a transimpedance gain defined in Equation 3:VOUT=IDAC*[(RF+N*RL)]/2  Eq. 3Under the condition of RF>>N*RL, as set forth in U.S. Pat. No. 7,119,611, VOUT=IDAC*RF/2. Second, the current I generated by transistor 46 has to flow through series resistor RS, which results not only in a voltage divider, but also a mismatch of VDS (drain to source voltage) between transistor 46 and variable replica stage 47, which causes line driver 40 to produce a nonlinear gain and the distortion of matching ratio N.
The problems associated with line driver 40 are described with reference to FIGS. 11(A) and 11(B). FIG. 11(A) is a simplified circuit showing portions of line driver 40 and depicts the cause of ½ gain issue. For a unit of current I flowing through transistor 46, there will be a N*I copy flowing out of variable replica stage 47, making the total current flow through load resistance RL equal to (N+1)*I. This current results an equivalent resistor of (N+1)*RL. Notice that series resister RS is also equivalent to (N+1)*RL, and as a result a voltage divider is formed that divides the gain by 2. So the output voltage VOUT is half of amplifier output, as shown in 11(B) and set forth in Equation 4:VOUT=½VDAC=½IDAC*RF  Eq. 4
What is needed is a line driver with on-chip termination that overcomes the gain issues and other problems associated with prior art line drivers.